1. Field of the Invention
The present invention relates to a counter, and more particularly, to a counter having improved counting speed.
2. Description of the Related Art
As system-on-chip (SOC) systems have become faster, the core of each chip has been specially developed. In general, counters are used in most semiconductor devices and play an important role in determining delay between pipes. A short counter delay helps reduce the burden of combinational logic due to delay time, ensuring an operational margin in the design of the semiconductor circuit.
FIG. 1 is a block diagram of a circuit of a general synchronous counter. Referring to FIG. 1, a synchronous counter 100 is set or reset in response to a reset signal RN and includes first through fourth flip flops 110, 120, 130, 140 and first and second combinational logic blocks 150 and 160 which operate in response to a clock signal CK. The first flip flop 110 receives an inversion signal BOUT1 of a first output signal OUT1 through an input terminal D, and the second flip flop 120 receives an output signal OUT1 of the first flip flop 110 through an input terminal D. The third flip flop 130 receives a second output signal OUT2 through an input terminal D via the first combinational logic block 150. The fourth flip fop 140 receives the third output signal OUT3 through an input terminal D via the second combinational logic block 160. Signals OUT1 through OUT4 indicate the least significant bit (LSB) through most significant bit (MSB) of the counter 100. Here, the counter 100 is a four-bit counter.
Such a synchronous counter includes the combinational logic blocks 150 and 160, as well as the flip flops 110 through 140, which cause a predetermined delay logic blocks when determining the next state of the counter 100. Further, it is difficult to determine the maximum frequency of the counter 100 because of these combinational logic blocks 150 and 160. That is, the combinational logic blocks 150 and 160, such as adders used in determining the LSB of the counter 100, are required in order to determine the MSB of the next state of the counter 100. For this reason, an increase in the number of bits of the counter 100 results in an increase in delay time.
FIG. 2 is a timing diagram of the operation of the synchronous counter 100 of FIG. 1. In the synchronous counter 100, the output signals OUT1 through OUT4 are all output almost at the same time, but not until after a delay of about 1.5 ns from receiving a clock signal CK.
FIG. 3 is a block diagram of a circuit of a general four-bit non-synchronous counter. Referring to FIG. 3, a non-synchronous counter 300 is set or reset in response to a reset signal RN, and includes a flip flop 310 which operates in response to a clock signal CK, and flip flops 320, 330 and 340 which operate in response to output signals OUT1 through OUT3 output from the flip flops 310, 320 and 330. The flip fops 310, 320, 330 and 340 receive inversion signals BOUT1 through BOUT4 of the output signals OUT1 through OUT4 through an input terminal D. The output signals OUT1 through OUT4 indicate the LSB through MSB of the counter 300.
In such a non-synchronous counter, the output signal of one flip flop is determined by the output signal of the previous flip flop, and thus the generated output signal is delayed for a predetermined time.
FIG. 4 is a timing diagram of the non-synchronous counter 300 of FIG. 3. Referring to FIG. 4, the final state of the counter 300 is at a point when the MSB of the counter is determined and a fourth output signal OUT4 is output. Output signals OUT1 through OUT4 are sequentially generated, and in particular the fourth output signal OUT4 is not output until a delay of about 1 ns after a clock signal CK is input. Also, the fourth output signal OUT4 is generated after one period of the clock signal CK, which is a malfunction of the counter 300.
As described above, both a synchronous counter and a non-synchronous counter have a predetermined delay, which must be reduced.